LDPC Decoder of High Speed Multi-Rate DVB-S2 Based on FPGA
نویسندگان
چکیده
منابع مشابه
A pipelined semi-parallel LDPC Decoder architecture for DVB-S2
The implementation of an LDPC Decoder for the DVB-S2 standard is a challenging task, specially because of 1) the large parity-check matrices and 2) the iterative decoding algorithm, which may represent a bottleneck within the receiver data flow. This paper presents a pipelined architecture for LDPC decoding based on a semi-parallel implementation of the Minimum-Sum algorithm, a simplification o...
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ژورنال
عنوان ژورنال: Xibei Gongye Daxue Xuebao/Journal of Northwestern Polytechnical University
سال: 2019
ISSN: 1000-2758,2609-7125
DOI: 10.1051/jnwpu/20193720299